OpenCores: A-Z80 CPU
Comments
JPLeRouzic
retrac
Iverilog is a Verilog simulator. [1] Yosys [2] can synthesize Verilog to a variety of things, including simplified Verilog, cell netlists for ASICs and FPGAs (requiring further conversion), and also directly to the bytestream, for some Lattice FPGAs. Both are fully open source tools. Not as sophisticated as the commercial tools, and the Verilog dialect that is common between the two, is quite minimal, almost painfully so.
But it works! A couple years ago I tested yosys with some code a little simpler than yours - a Verilog PDP-8 processor. Yosys turned it into a network of about 100 flip-flops and 800 NAND gates that, in principle, could be wired up out of TTL chips or made into an IC.
rowanG077
Just use any editor + yosys and nextpnr. You can buy an FPGA like the lattice ICE40 or Lattice ECP5 for cheap.
weebull
I recommend Emacs + verilog-mode.
boricj
The Z80 in its original form has apparently reached EOL status:
- https://hackaday.com/2024/04/19/end-of-life-for-z80-cpu-and-...
I wanted to have a try at Verilog for CPU design. As I am a noob in this area, I decided to try to compile a 6502 core [0] on CPLDs. The first problem I had was that it seems there are very few free Verilog IDEs on Linux. I ended up using the one from Intel. So now I had to use Intel's CPLDs and anyway, the CPLDs used by Arlet Ottens do not exist anymore. Then while this 6502 core is not that old, it doesn't compile on the Intel IDE, despite several people having used the core years ago.
So is there a smooth way to edit 6 years old Verilog files on Linux without being linked to some manufacturer?
[0] https://github.com/Arlet/cpld-6502